Micronics PCI/ISA System Board D6-IN Informazioni Techniche Pagina 44
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Twister LX System Board Manual
Chapter 4: The BIOS Setup Utility
42
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the
PCI IDE interface. IDE accesses are posted in the CPU to
PCI buffers, for cycle optimization.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS
ROM at F0000h-FFFFFh, resulting in better system per-
formance. However, if any program writes to this memory
area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS
ROM at C0000h to C7FFFh, resulting in better video
performance. However, if any program writes to this
memory area, a system error may result.
Video RAM Cacheable
Enable or disable the caching of the video RAM. The
default settings is Disabled.
8-Bit/16-Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles be-
tween PCI-originated I/O cycles to the ISA bus. This
delay takes place because the PCI bus is so much faster
than the ISA bus. These two fields let you add recovery
time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for the ISA
adapter ROM. When this area is reserved, it cannot be
cached.
- Twister LX Pentium II 1
- Portions of the Manual 2
- Trademarks 2
- Copyright Notices 2
- Table of Contents 3
- List of Figures 6
- List of Tables 6
- Introduction 7
- Features 8
- Software Compatibility 9
- Before You Begin 10
- Quick Installation 11
- Chapter 1: Quick Installation 12
- Configuring the Twister 13
- Twister LX System Board 14
- Jumper Settings 15
- Installing the Twister 19
- System Memory 21
- Memory Configurations 22
- CPU Installation 24
- Installing a CPU 25
- Retention Base 25
- CPU Installation Overview 27
- Install to 28
- Removing DIMMs 29
- The BIOS Setup Utility 33
- Figure 4-1: Power-Up Screen 34
- Running the Setup Program 35
- Date and Time 36
- Hard Disks Setup 36
- Diskette A or B 37
- Base/Extended/Other Memory 37
- Virus Warning 38
- CPU Internal Cache 38
- External Cache 38
- Gate A20 Option 40
- Typematic Rate Setting 40
- Security Option 40
- PCI/VGA Palette Snoop 40
- OS Select for DRAM>64MB 41
- Video BIOS Shadow 41
- Chipset Features Setup 42
- Power Management 46
- PM Control By APM 47
- Video OFF Method 47
- Video OFF After 47
- Modem Use IRQ 47
- Doze Mode 47
- IRQ 8 Clock Event 49
- Reload Global Timer Events 49
- PnP OS Installed 50
- Resources Controlled By 50
- Reset Configuration Data 51
- Assigned To 51
- PCI IDE Map To 52
- Used Memory Base Address 52
- Used Memory Length 52
- IDE HDD Block Mode 53
- USB Keyboard Support 54
- KBC Input Clock 54
- Onboard FDC Controller 54
- UR2 Mode 55
- Onboard Parallel Port 55
- Parallel Port Mode 55
- ECP Mode Use DMA 55
- Supervisor Password 56
- User Password 56
- IDE HDD Auto Detection 57
- HDD Low Level Format 58
- Save and Exit Setup 59
- Exit Without Saving 59
- Special Features 61
- Ultra DMA/33 IDE 62
- Universal Serial Bus (USB) 62
- Appendix 63
- Environmental Specifications 65
- Battery Disposal 66
- Technical Support 67
- Appendix B: POST Messages 70
- Updating the System BIOS 75
- Non-Warranty Service 78
- FCC Statement 79
- Glossary 80
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